Power gating is used for reducing LEAKAGE POWER by switching off power supply to the non operational power domain of the chip during certain mode of operation. Header and footer switches, isolation cells and state retention flip flips (SRFFs) are used for implementing power gating.
Clock gating is used for reducing DYNAMIC POWER by controlling switching activities on the clock path. Generally Gate or Latch or FF based clock gating cells are used for implementing clock gating.