层次设计教学:https://blog.csdn.net/m0_37652453/article/details/105326243
module yyc2018113559_2_1(clk,en,Q); //六进制计数器input clk,en; //clk为时钟output reg[2:0] Q;always@(posedge clk)beginif(en==1'b1) //en等于1时计数beginif(Q<3'd5) //小于5就加1Q<=Q+1'b1;else //大于5进1位Q<=0;endelse //en为0时Q<=Q;endendmodule module yyc2018113559_2_2(X,bits); //译码器,实现同时间数码管外围依次点亮input[2:0] X; //输入X从000到101,共6位output reg[5:0] bits; //输出实现每段只亮一次always@(X)begincase(X) //同时刻只亮一段,其余熄灭3'd0:bits=6'b00_0001;3'd1:bits=6'b00_0010;3'd2:bits=6'b00_0100;3'd3:bits=6'b00_1000;3'd4:bits=6'b01_0000;3'd5:bits=6'b10_0000;default:bits=6'b00_0000;endcaseendendmodule