Express or Compute Express Link。CDATCoherent Device Attribute Table, a table describing performance characteristics
of a CXL device or a CXL switch.CEDTCXL Early Discovery TableCHBCRCXL Host Bridge Component RegistersCXLCompute Express Link, a low-latency, high-bandwidth link that supports dynamic protocol muxing of coherency, memory access, and IO protocols, thus enabling attachment of coherent accelerators or memory devices.CXL.cacheAgent coherency protocol that supports device caching of Host memoryCXL.ioPCIe-based non coherent I/O protocol with enhancements for accelerator supportCXL.memMemory access protocol that supports device-attached memoryDCOHThis refers to the Device Coherency agent on the device that is responsible for resolving coherency with respect to device caches and managing Bias statesHDMHost-managed Device Memory. Device-attached memory mapped to system coherent address space and accessible to Host using standard write-back semantics. Memory located on a CXL device can either be mapped as HDM or PDM.PDMPrivate Device memory. Device-attached memory not mapped to system address space or directly accessible to Host as cacheable memory. Memory located on PCIe devices is of this type. Memory located on a CXL device can either be mapped as PDM or HDM.Home AgentThis is the agent on the Host that is responsible for resolving system wide coherency for a given address2：CXL概述
定义：CXL(Compute Express Link)是支持加速设备和内存设备的动态复用协议。（accelerators指有独立大内存的外接设备，如GPU,Net Adapter等）。
关键点：CXL为加速设备提供了一个低延时高带宽的途径访问系统，也加速了系统访问CXL设备上内存。
说人话：CXL是基于PCIE来做，最大的特点是开放了内存接口，往后可以实现像USB一样外接内存。这是2015年接触服务器以来最惊喜的技术，往后发展还有可能实现CPU和内存的分离。彻底颠覆数据中心的架构。
1）事务层协议 CXL.ioCXL.io is required for discovery and enumeration, error report, and host physical address (HPA) lookup.
CXL.cache设备访问host端内存。
CXL.memhost端访问设备内存。
2）Flex Bus
Flex Bus port设计为在PCIE和CXL二选一的高带宽链路，这个选择在link training阶段根据alternate protocol和端口外接的设备进行协商。
CXL工作在PCIE electrical层上，CXL.io个关于设备的配置资源申请等和PCIE复用，CXL.mem,CXL.cache是独立协议，但最后汇集到PCIE物理层。
3）CXL 经典设备类型
4）：Bias Based Coherency Model
The Bias Based coherency model defines two states of bias for device-attached memory:
Host Bias state:
相对于设备，内存就是主机侧内存，访问需要事务。
Device Bias state,:
主机cache中无对应line，设备可以不用事务情况下直接访问。
To maintain Bias modes, a Type 2 CXL Device will:
• Implement the Bias Table which tracks Bias on a page granularity which can be cached in the device using a Bias Cache.
• Build support for Bias transitions using a Transition Agent (TA). This essentially
looks like a DMA engine for “cleaning up” pages, which essentially means to flush
the host’s caches for lines belonging to that page.
• Build support for basic load and store access to accelerator local memory for the
benefit of the Host.