zynq7010是一款全可编程SoC芯片,具有高度灵活性和可扩展性。本文将从多个方面对zynq7010的参数进行详细介绍。
一、器件规格
zynq7010基于ARM Cortex-A9 MPCore处理器,具有256MB DDR3 SDRAM和16MB QSPI Flash存储器。其主要器件规格如下:
#define CONFIG_ARMV7_MPU #define CONFIG_SYS_FSL_DDRC_PHY_G1 #define CONFIG_ZYNQ_SERIAL_UART0 #define CONFIG_ZYNQ_PL310_ERRATA_769419 #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_ICACHE_OFF #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 #define CONFIG_CMD_EXT4 #define CONFIG_CMD_MMC #define CONFIG_CMD_MMC_WRITE #define CONFIG_CMDLINE_EDITING #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_MENU #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttyPS0,115200 " "root=/dev/mmcblk0p2 rw rootwait" #define CONFIG_BOOTCOMMAND "mmc dev 0; mmc part; " "mmc read 0 0x1000 0x2000; env import " "-t 0x1000 0x2000" #define CONFIG_EXTRA_ENV_SETTINGS "kernel_image=uImage " "ramdisk_image=uramdisk.image.gz " "fdt_addr=0x1800000 " "fdt_image=my_fdt.dtb " "serial_udev=1 " "console=ttyAMA0,115200 earlycon " "stdin=serial " "stdout=serial " "stderr=serial "
其中,CONFIG_ARMV7_MPU表示zynq7010支持ARMv7架构的内存保护单元(Memory Protection Unit);CONFIG_ZYNQ_PL310_ERRATA_769419表示zynq7010存在PL310 Errata 769419,需要特别修复;CONFIG_CMD_ELF、CONFIG_CMD_EXT2、CONFIG_CMD_EXT4等表示zynq7010支持的命令和文件格式。
二、处理器系统
zynq7010的处理器系统包括ARM Cortex-A9 MPCore处理器、AXI总线、内存控制器和DMA控制器等。
1. ARM Cortex-A9 MPCore处理器
ARM Cortex-A9 MPCore处理器是ARM公司的多核心处理器IP,用于集成在SoC芯片中,并拥有非常高的灵活性。zynq7010中采用的是双核处理器,每个核心的主频为667MHz。
#define XPS_BOARD_ZC702 #define XPS_BOARD_ZED #define XPS_BOARD_ZC706 #define XPS_BOARD_MINIITX #define XPS_BOARD_MICROZED #define XPS_BOARD_ZYBO #define DCC_SILENT #define CONFIG_COMMON_ENV_SETTINGS "ethaddr=00:0a:35:00:00:00 " "eth1addr=00:0a:35:00:00:01 " "ethact=GEM0 " "serverip=192.168.0.10 " "ipaddr=192.168.0.11 " "netmask=255.255.255.0 " "gatewayip=192.168.0.1 " "uboot=u-boot.elf " "script=boot.scr " "bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait " "loadbootscript=" "fatload mmc 0 ${scriptaddr} ${script} && " "source ${scriptaddr} " "loaduimage=" "fatload mmc 0 ${loadaddr} ${uimage} " "loadfdt=" "fatload mmc 0 ${fdtaddr} ${fdtfile} " "mmcboot=" "mmc dev ${mmcdev} && " "mmc read ${loadaddr} 0x800 0x2000 && " "mmc read ${fdtaddr} 0x2800 0x800 && " "bootm ${loadaddr} - ${fdtaddr} " "bootcmd=run loadbootscript; run mmcboot; " "autoload=no " "ethaddr=00:0a:35:00:01:22 " "autostart=no " "bootdelay=3 " "filesize=0x800000 "
2. AXI总线
AXI总线是ARM公司推出的高性能、低功耗的内部总线,用于处理器和外设之间的通信。zynq7010中采用了AXI总线作为内部总线,以提高系统性能。
#include #include int arch_misc_init(void) { ps7_init(); return 0; } #if defined(CONFIG_CMD_PCI) && defined(CONFIG_PCI) #include#define PCIBIOS_MIN_MEM 0x80000000 #define PCIBIOS_MIN_IO 0x01000000 static struct pci_controller pci_hose; #endif/* (CONFIG_CMD_PCI && CONFIG_PCI) */ int board_early_init_f(void) { #if defined(CONFIG_CMD_PCI) && defined(CONFIG_PCIE_XILINX) pci_hose.first_busno = 0; pci_hose.last_busno = 0xff; pci_hose.region_count = 1; pci_hose.region[0].phys_start = CONFIG_PCIE_PHYS_BASE1; pci_hose.region[0].bus_start = 0; pci_hose.region[0].size = CONFIG_PCIE_PHYS_SIZE1; pci_set_region(&pci_hose.region[0], CONFIG_PCIE_PHYS_BASE1); pci_hose.cfg_addr = (void *)CONFIG_PCI_ADDR; pci_hose.cfg_data = (void *)(CONFIG_PCI_ADDR + 4); pci_hose.probe_irq = xilinx_pcie_probe_irq; pci_hose.setup_hose = xilinx_pcie_setup_hose; pci_hose.get_hose_li = (void (*)(struct pci_controller *, unsigned long *, unsigned int *))xilinx_pcie_get_hose_li; xilinx_pcie_init_hose(&pci_hose); #endif return 0; }
3. 内存控制器
内存控制器用于管理SoC芯片中的内存资源,包括总线接口、控制逻辑和物理内存组织等。zynq7010采用的是DDR3 SDRAM,具有256MB容量。
#define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ENV_IS_IN_MMC 1 #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_CMD_NAND #define CONFIG_JFFS2_NAND #define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_CMD_USB #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) #define CONFIG_EXTRA_ENV_SETTINGS "uenv_size=4096 " "ethaddr=00:0a:35:00:00:00 " "serverip=192.168.1.100 " "ipaddr=192.168.1.10 " "netmask=255.255.255.0 " "gatewayip=192.168.1.1 " "hostname=microzed " "rootdir=/var/ftp/hdd1/targetfs " "ethact=gem0 " "usb_boot=" "echo 'Booting from USB';" "setenv bootargs root=/dev/sda2 rw rootwait console=ttyPS0,115200;" "load usb 0:1 ${kernel_addr_r} ${uenv_addr_r} ${filesize} && env import -t $uenv_addr_r $uenv_size;" "load usb 0:1 ${fdt_addr_r} ${fdt_file} && bootm ${kernel_addr_r} - ${fdt_addr_r}" " " "usb_flash_boot=" "echo 'Booting from USB Flash';" "setenv bootargs root=/dev/sda2 rw rootwait console=ttyPS0,115200;" "load usb 0:1 ${kernel_addr_r} ${uenv_addr_r} ${filesize} && env import -t $uenv_addr_r $uenv_size;" "load usb 0:1 ${fdt_addr_r} ${fdt_file} && bootm ${kernel_addr_r} - ${fdt_addr_r}" " " "set_fdt=" "if test ${board_rev} = 'C'; then" "setenv fdt_file zynq-microzed-7010-revC.dtb;" "else" "setenv fdt_file zynq-microzed-7010.dtb;" "fi" " " "tftp_flash=" "setenv fsize; setenv load_addr 0x1000000; setenv img zynq-microzed-7010.bin;" "tftp $load_addr $img && setenv fsize ${filesize} && echo Fsize=${fsize} bytes &&" "mmc dev 0 && mmc write $load_addr 0 ${fsize} && echo 'Flash Complete'" " " "mmc_boot=" "echo 'Booting from MicroSD Card ...';" "setenv bootargs root=/dev/mmcblk0p2 rw rootwait console=ttyPS0,115200;" "load mmc 0:2 ${kernel_addr_r} ${uenv_addr_r} /boot/uEnv.txt && env import -t $uenv_addr_r $uenv_size;" "load mmc 0:2 ${kernel_addr_r} /boot/zImage ${filesize} && " "load mmc 0:2 ${fdt_addr_r} /boot/${fdt_file} ${filesize} && bootm ${kernel_addr_r} - ${fdt_addr_r}" " " "nandboot=" "echo 'Booting from NAND Flash ...';" "setenv bootargs root=/dev/mtdblock2 rw rootwait console=ttyPS0,115200;" "nand read ${kernel_addr_r} 0x100000 0x600000 && nand read ${fdt_addr_r} 0x700000 0x100000 && bootm ${kernel_addr_r} - ${fdt_addr_r}" " " #define MEMTEST_START 0x00100000 #define MEMTEST_END 0x01000000
4. DMA控制器
DMA控制器用于管理SoC芯片与外设之间数据传输的控制逻辑,提高数据传输效率。zynq7010中集成了DMA控制器,可以支持高速、大容量数据传输。
#include #include#include #include #include #include #include /* FPD SLCR registers */ #define FPD_SLCR_BASEADDR 0xF0000000 #define FPD_LPD_IOU_SLCR_OFFSET 0x1000 #define FPD_SLCR_LOCK_OFFSET 0x4 #define FPD_SLCR_UNLOCK_OFFSET 0x8 #define FPD_SLCR_LOCKSTA_OFFSET 0xC static inline u32 zynq_slcr_read(u32 offset) { return readl(FPD_SLCR_BASEADDR + FPD_LPD_IOU_SLCR_OFFSET + offset); } static inline void zynq_slcr_write(u32 val, u32 offset) { writel(val, FPD_SLCR_BASEADDR + FPD_LPD_IOU_SLCR_OFFSET + offset); } /* * SATA driver interface functions */ static void zynq_sata_init(void); static int zynq_sata_recv_fis(drv_hc_t *hcc, struct sata_fis_d2h_reg **fis, u32 tag); static int zynq_sata_send_fis(drv_hc_t *hcc, struct sata_fis_h2d_reg *fis); static int zynq_sata_hard_reset(drv_hc_t *hcc); static int zynq_sata_mode_detect(drv_hc_t *hcc); static int z