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verilog数码管倒计时(Verilog——7段数码管译码器)

时间:2023-05-03 14:59:31 阅读:122068 作者:4225

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组合逻辑代码设计

moduleseg_dec(num,a_g ); input[3:0] num; output[6:0] a_g; //a_g[6:0]-(a、b、c、d、e、f、reg[6:0] a_g; always@(num ) begincase ) num )通过case语句实现组合逻辑4(d0:begina_g=7) b111_1110; end4' d 1: begina _ g=7' b011 _ 0000; end4' d 2: begina _ g=7' b110 _ 1101; end4' d : begina _ g=7' b111 _ 1100; end4' d 4: begina _ g=7' b011 _ 0011; end4' d 5: begina _ g=7' b101 _ 1011; end4' d 6: begina _ g=7' b101 _ 1111; end4' d 7: begina _ g=7' b111 _ 0000; end4' d 8: begina _ g=7' b111 _ 1111; end4' d 9: begina _ g=7' b111 _ 1011; end default : begina _ g=7' b000 _ 0001; end//num超过(0-9)时,用default批量处理,显示为中棒; endcaseendendmodule

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